US 12,249,574 B2
Interconnect structure of semiconductor device and method of forming same
Tung Ying Lee, Hsinchu (TW); and Bo-Jiun Lin, Jhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 14, 2022, as Appl. No. 17/576,137.
Claims priority of provisional application 63/226,843, filed on Jul. 29, 2021.
Claims priority of provisional application 63/214,276, filed on Jun. 24, 2021.
Prior Publication US 2022/0415785 A1, Dec. 29, 2022
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/52 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a dielectric layer over a substrate;
patterning the dielectric layer to form an opening in the dielectric layer;
forming a barrier/adhesion layer along a bottom and sidewalls of the opening, a material of the barrier/adhesion layer having a chemical formula MXn, with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2, wherein forming the barrier/adhesion layer comprises:
depositing a layer of the transition metal element along the bottom and the sidewalls of the opening; and
after depositing the layer of the transition metal element, performing a chalcogen treatment on the layer of the transition metal element; and
depositing a conductive layer over the barrier/adhesion layer in the opening.