| CPC H01L 23/49816 (2013.01) [H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 25/0657 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01)] | 13 Claims |
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1. A semiconductor device comprising:
a substrate including a redistribution layer, a ball land provided on a bottom surface of the redistribution layer, a passivation layer surrounding the ball land on the bottom surface of the redistribution layer and spaced apart from the ball land by a space region formed between the passivation layer and the ball land, and a signal wiring line provided in the redistribution layer and on the ball land;
a semiconductor chip mounted on the substrate; and
an external terminal adhered to the ball land,
wherein the signal wiring line comprises:
a first wiring pattern extending in a first direction perpendicular to one side surface of the semiconductor chip; and
a support pattern disposed under the one side surface of the semiconductor chip, the first wiring pattern having a first width in a second direction, and the support pattern having a second width in the second direction, wherein the second width is greater than the first width, and the second direction is parallel to a bottom surface of the substrate and perpendicular to the first direction,
wherein the space region is disposed under the one side surface of the semiconductor chip; and
wherein the support pattern extends from the passivation layer onto the ball land across the space region below the one side surface of the semiconductor chip in a plan view.
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