US 12,249,562 B2
Intelligent power module containing exposed surfaces of transistor die supporting elements
Zhiqiang Niu, Santa Clara, CA (US); Bum-Seok Suh, Seongnam (KR); Junho Lee, Suwon-si (KR); Jong-Mu Lee, Yongin-si (KR); and Xiaorong Ge, Pleasanton, CA (US)
Assigned to ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP, Toronto (CA)
Filed by ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP, Toronto (CA)
Filed on Mar. 1, 2022, as Appl. No. 17/683,354.
Prior Publication US 2023/0282554 A1, Sep. 7, 2023
Int. Cl. H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H02P 29/00 (2016.01)
CPC H01L 23/49575 (2013.01) [H01L 23/3107 (2013.01); H01L 23/49555 (2013.01); H01L 23/49562 (2013.01); H01L 24/48 (2013.01); H01L 2224/48137 (2013.01); H02P 29/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An intelligent power module (IPM) for driving a motor, the IPM comprising:
one or more transistor die supporting elements;
one or more transistors mounted on the one or more transistor die supporting elements;
a first integrated circuit (IC) die supporting element;
a first IC disposed on the first IC die supporting element;
a plurality of bond wires connecting the first IC to at least one of the one or more transistors;
a plurality of leads;
one or more slanted sections connecting the one or more transistor die supporting elements to the plurality of leads; and
a molding encapsulation completely enclosing the one or more transistors, the first IC die supporting element, the first IC, and the one or more slanted sections;
wherein a respective bottom surface of each of the one or more transistor die supporting elements are exposed from a bottom of the molding encapsulation;
wherein the one or more transistor die supporting elements comprise:
a first, second, third and fourth transistor die supporting elements separated from one another; and
wherein the one or more transistors comprise:
a first transistor attached to the first transistor die supporting element;
a second transistor attached to the second transistor die supporting element;
a third transistor attached to the third transistor die supporting element; and
a fourth, fifth, and sixth transistors attached to the fourth transistor die supporting element.