US 12,249,550 B2
Semiconductor package and method manufacturing the same
Feng-Cheng Hsu, New Taipei (TW); and Shin-Puu Jeng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 4, 2022, as Appl. No. 17/736,104.
Application 17/736,104 is a continuation of application No. 16/907,180, filed on Jun. 20, 2020, granted, now 11,355,474.
Application 16/907,180 is a continuation of application No. 15/854,704, filed on Dec. 26, 2017, granted, now 10,727,198, issued on Jul. 28, 2020.
Claims priority of provisional application 62/527,047, filed on Jun. 30, 2017.
Prior Publication US 2022/0262767 A1, Aug. 18, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01); H01L 21/768 (2006.01); H01L 23/29 (2006.01)
CPC H01L 23/3135 (2013.01) [H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3107 (2013.01); H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 25/0652 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 21/76898 (2013.01); H01L 23/293 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/13101 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1047 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/18161 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
an insulating encapsulation having a first side and a second side opposite to the first side;
an integrated circuit component, encapsulated in the insulating encapsulation and having a top surface exposed by the first side of the insulating encapsulation;
a plurality of conductive pillars, arranged aside of and electrically connected to the integrated circuit component and each having an end surface exposed by the second side of the insulating encapsulation;
a glue material, encapsulated in the insulating encapsulation, a sidewall of the integrated circuit component being completely separating from the insulating encapsulation by the glue material, wherein at least one first conductive pillar of the plurality of conductive pillars and the insulating encapsulation are separated by the glue material; and
at least two semiconductor devices, located over the top surface of the integrated circuit component and electrically communicated to each other through the integrated circuit component.