US 12,249,545 B2
Integrated circuit device
Purakh Raj Verma, Singapore (SG); Kuo-Yuh Yang, Hsinchu County (TW); Chia-Huei Lin, Hsinchu (TW); and Chu-Chun Chang, Kaohsiung (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Aug. 19, 2021, as Appl. No. 17/407,157.
Application 17/407,157 is a continuation in part of application No. 16/886,721, filed on May 28, 2020, granted, now 11,127,700.
Prior Publication US 2021/0384093 A1, Dec. 9, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/10 (2006.01); H10B 61/00 (2023.01); H10B 63/10 (2023.01); H10N 50/80 (2023.01); H10N 70/00 (2023.01)
CPC H01L 23/10 (2013.01) [H10B 61/00 (2023.02); H10N 50/80 (2023.02); H10N 70/801 (2023.02); H10B 63/10 (2023.02)] 15 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
a substrate;
an integrated circuit area on the substrate, said integrated circuit area comprising a dielectric stack;
a seal ring disposed in said dielectric stack and around a periphery of said integrated circuit area;
a cap layer on the dielectric stack;
a trench around the seal ring and exposing a sidewall of said dielectric stack;
a memory storage structure disposed on said cap layer; and
a moisture blocking layer continuously covering said integrated circuit area and said memory storage structure, wherein said moisture blocking layer extends to said sidewall of said dielectric stack, thereby sealing a boundary between two adjacent dielectric films in said dielectric stack.