US 12,249,544 B2
Semiconductor device, method of manufacturing the same and electronic device including the device
Huilong Zhu, Poughkeepsie, NY (US)
Assigned to INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES, Beijing (CN)
Filed by INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES, Beijing (CN)
Filed on May 15, 2023, as Appl. No. 18/317,722.
Application 18/317,722 is a continuation of application No. 17/033,284, filed on Sep. 25, 2020, granted, now 11,695,074.
Application 17/033,284 is a continuation of application No. 15/720,913, filed on Sep. 29, 2017, granted, now 10,833,193, issued on Nov. 10, 2020.
Claims priority of application No. 201610872541.2 (CN), filed on Sep. 30, 2016; and application No. 201710530685.4 (CN), filed on Jun. 30, 2017.
Prior Publication US 2023/0369489 A1, Nov. 16, 2023
Int. Cl. H01L 21/8238 (2006.01); B82Y 10/00 (2011.01); G05B 23/02 (2006.01); G06T 19/00 (2011.01); H01L 21/02 (2006.01); H01L 21/223 (2006.01); H01L 21/225 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/324 (2006.01); H01L 21/822 (2006.01); H01L 21/8234 (2006.01); H01L 23/522 (2006.01); H01L 27/092 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/15 (2006.01); H01L 29/165 (2006.01); H01L 29/205 (2006.01); H01L 29/267 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/778 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H04N 7/18 (2006.01); H04N 23/698 (2023.01); G06F 3/04817 (2022.01); G06F 3/0482 (2013.01); G06V 20/40 (2022.01); H01L 21/3105 (2006.01); H04N 13/111 (2018.01); H04N 13/332 (2018.01); H04N 13/366 (2018.01); H04N 13/398 (2018.01); H04N 23/90 (2023.01)
CPC H01L 21/823885 (2013.01) [B82Y 10/00 (2013.01); G05B 23/0216 (2013.01); G06T 19/006 (2013.01); H01L 21/02532 (2013.01); H01L 21/02636 (2013.01); H01L 21/2236 (2013.01); H01L 21/2252 (2013.01); H01L 21/2253 (2013.01); H01L 21/2258 (2013.01); H01L 21/3065 (2013.01); H01L 21/3083 (2013.01); H01L 21/324 (2013.01); H01L 21/8221 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/82345 (2013.01); H01L 21/823475 (2013.01); H01L 21/823487 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823842 (2013.01); H01L 21/823864 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 23/5221 (2013.01); H01L 27/092 (2013.01); H01L 27/0925 (2013.01); H01L 29/04 (2013.01); H01L 29/0638 (2013.01); H01L 29/0653 (2013.01); H01L 29/0676 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/1054 (2013.01); H01L 29/1083 (2013.01); H01L 29/1095 (2013.01); H01L 29/152 (2013.01); H01L 29/165 (2013.01); H01L 29/205 (2013.01); H01L 29/267 (2013.01); H01L 29/41741 (2013.01); H01L 29/42376 (2013.01); H01L 29/42392 (2013.01); H01L 29/45 (2013.01); H01L 29/66431 (2013.01); H01L 29/66439 (2013.01); H01L 29/66462 (2013.01); H01L 29/66469 (2013.01); H01L 29/66522 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66666 (2013.01); H01L 29/66712 (2013.01); H01L 29/66742 (2013.01); H01L 29/775 (2013.01); H01L 29/7788 (2013.01); H01L 29/7813 (2013.01); H01L 29/7827 (2013.01); H01L 29/7848 (2013.01); H01L 29/78618 (2013.01); H01L 29/78642 (2013.01); H01L 29/78696 (2013.01); H04N 7/181 (2013.01); H04N 23/698 (2023.01); G05B 2219/32014 (2013.01); G06F 3/04817 (2013.01); G06F 3/0482 (2013.01); G06V 20/40 (2022.01); G06V 20/44 (2022.01); G06V 2201/06 (2022.01); H01L 21/31053 (2013.01); H01L 21/823828 (2013.01); H01L 29/0649 (2013.01); H04N 13/111 (2018.05); H04N 13/332 (2018.05); H04N 13/366 (2018.05); H04N 13/398 (2018.05); H04N 23/90 (2023.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a first device and a second device formed on the substrate, wherein each of the first device and the second device comprises:
a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence; and
a gate stack surrounding a periphery of the channel layer,
wherein the semiconductor device further comprises a first dielectric film formed on the first device and a second dielectric film formed on the second device, and the first dielectric film is in contact with the second dielectric film, and
wherein the first dielectric film is in contact with the second dielectric film in a direction parallel to a surface of the substrate, an orthogonal projection of the first dielectric film on the substrate overlaps at least partially with an orthogonal projection of the second dielectric film on the substrate.