US 12,249,541 B2
Vertical edge blocking (VEB) technique for increasing patterning process margin
Leonard P. Guler, Hillsboro, OR (US); Chul-Hyun Lim, Albuquerque, NM (US); Paul A. Nyhus, Portland, OR (US); Elliot N. Tan, Portland, OR (US); and Charles H. Wallace, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 12, 2023, as Appl. No. 18/096,351.
Application 18/096,351 is a division of application No. 16/435,259, filed on Jun. 7, 2019, granted, now 11,594,448.
Prior Publication US 2023/0145089 A1, May 11, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01)
CPC H01L 21/76816 (2013.01) [H01L 21/31144 (2013.01); H01L 21/76877 (2013.01); H01L 29/41725 (2013.01); H01L 29/42316 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first interlayer dielectric (ILD);
a grid of source/drain (S/D) contacts and gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in a 1:1 alternating pattern along a first direction and along a second direction, the second direction orthogonal to the first direction, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that an opening defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts;
a mask layer partially filling a first opening over a first gate contact; and
a fill metal filling a second opening over a second gate contact that is adjacent to the first gate contact.