| CPC H01L 21/6835 (2013.01) [H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 24/13 (2013.01); H01L 28/87 (2013.01); H01L 2221/68304 (2013.01); H01L 2221/68363 (2013.01); H01L 2221/68368 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/0346 (2013.01); H01L 2224/03622 (2013.01); H01L 2224/03845 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/05657 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/05684 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/13006 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/80379 (2013.01); H01L 2224/808 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/83005 (2013.01)] | 20 Claims |

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1. A method for forming a semiconductor structure, comprising:
forming a contact feature over an insulating layer;
forming a first passivation layer over the contact feature;
etching the first passivation layer to form a trench exposing the contact feature;
forming an oxide layer over the contact feature and the first passivation layer and in the trench;
forming a first non-conductive structure over the oxide layer;
patterning the first non-conductive structure to form a gap;
filling a conductive material in the gap to form a first conductive feature, wherein the first non-conductive structure and the first conductive feature form a first bonding structure; and
attaching a carrier substrate to the first bonding structure via a second bonding structure over the carrier substrate.
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