US 12,249,514 B2
Carbon based depositions used for critical dimension control during high aspect ratio feature etches and for forming protective layers
Jon Henri, West Linn, OR (US); Karthik S. Colinjivadi, Dublin, CA (US); Francis Sloan Roberts, Portland, OR (US); Kapu Sirish Reddy, Portland, OR (US); Samantha Siamhwa Tan, Fremont, CA (US); Shih-Ked Lee, Fremont, CA (US); Eric Hudson, Berkeley, CA (US); Todd Shroeder, Sherwood, OR (US); Jialing Yang, Sherwood, OR (US); and Huifeng Zheng, Beaverton, OR (US)
Assigned to Lam Research Corporation, Fremont, CA (US)
Appl. No. 17/439,748
Filed by Lam Research Corporation, Fremont, CA (US)
PCT Filed Mar. 16, 2020, PCT No. PCT/US2020/022994
§ 371(c)(1), (2) Date Sep. 15, 2021,
PCT Pub. No. WO2020/190878, PCT Pub. Date Sep. 24, 2020.
Claims priority of provisional application 62/961,061, filed on Jan. 14, 2020.
Claims priority of provisional application 62/856,595, filed on Jun. 3, 2019.
Claims priority of provisional application 62/819,936, filed on Mar. 18, 2019.
Prior Publication US 2022/0199417 A1, Jun. 23, 2022
Int. Cl. H01L 21/311 (2006.01); H01J 37/32 (2006.01); H01L 21/02 (2006.01)
CPC H01L 21/31116 (2013.01) [H01J 37/32935 (2013.01); H01L 21/02115 (2013.01); H01J 2237/3321 (2013.01); H01J 2237/3347 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor substrate, the method comprising:
(a) vertical etching a feature having sidewalls and a depth into one or more layers formed on the semiconductor substrate;
(b) depositing an amorphous carbon liner onto the sidewalls of the feature; and
(c) iterating (a) and (b), wherein with each iteration of (a), the depth of the feature is vertical etched deeper into the one or more layers, while the deposited amorphous carbon liner resists lateral etching of the sidewalls of the feature, and wherein with each iteration of (b), the deposited amorphous carbon liner on the sidewalls of the feature is at least partially replenished.