CPC H01L 21/28506 (2013.01) [H01L 21/3213 (2013.01); H01L 21/7682 (2013.01); H01L 23/5329 (2013.01); H01L 23/544 (2013.01); H10B 12/00 (2023.02); H10B 12/09 (2023.02); H10B 12/50 (2023.02)] | 9 Claims |
1. A method of manufacturing a semiconductor structure, comprising:
forming a first conductive layer over a substrate;
forming a first dielectric layer over the first conductive layer;
form a first opening and a second opening in the first dielectric layer, wherein the first opening is in a pattern-dense region and the second opening is in a pattern-loose region;
depositing a plurality of first conductive plugs in the first opening;
depositing a lining layer over the first conductive plugs and the first dielectric layer, wherein the lining layer lines a sidewall and a bottom of the second opening;
forming a second conductive plug in a remaining portion of the second opening;
forming a second conductive layer over the lining layer and the second conductive plug;
depositing an energy removable layer in the first opening between the first conductive plugs; and
depositing a second dielectric layer in the first opening over the energy removable layer.
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