US 12,249,510 B2
Semiconductor device and method of manufacturing semiconductor device
Kazuki Kamimura, Matsumoto (JP); and Motoyoshi Kubouchi, Matsumoto (JP)
Assigned to FUJI ELECTRIC CO., LTD., Kawasaki (JP)
Filed by FUJI ELECTRIC CO., LTD., Kawasaki (JP)
Filed on Jul. 11, 2022, as Appl. No. 17/862,243.
Application 17/862,243 is a continuation of application No. 17/235,330, filed on Apr. 20, 2021.
Claims priority of application No. 2020-104316 (JP), filed on Jun. 17, 2020; and application No. 2020-211843 (JP), filed on Dec. 21, 2020.
Prior Publication US 2022/0351973 A1, Nov. 3, 2022
Int. Cl. H01L 29/10 (2006.01); H01L 21/22 (2006.01); H01L 21/265 (2006.01); H01L 21/268 (2006.01); H01L 21/8222 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 29/32 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/861 (2006.01)
CPC H01L 21/221 (2013.01) [H01L 21/26513 (2013.01); H01L 21/268 (2013.01); H01L 21/8222 (2013.01); H01L 27/0664 (2013.01); H01L 29/0623 (2013.01); H01L 29/1095 (2013.01); H01L 29/32 (2013.01); H01L 29/66136 (2013.01); H01L 29/66348 (2013.01); H01L 29/7397 (2013.01); H01L 29/8613 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate of a first conductivity type, having a first main surface and a second main surface that are opposite to each other;
a first semiconductor region of a second conductivity type, provided in the semiconductor substrate, closer to the first main surface than to the second main surface, the first semiconductor region having a first surface and a second surface that are opposite to each other, the second surface of the first semiconductor region being closer to the second main surface than is the first surface of the first semiconductor region;
a plurality of second semiconductor regions of the first conductivity type, selectively provided in the first semiconductor region at the first surface of the first semiconductor region;
a gate insulating film having a first surface and a second surface that are opposite to each other, the first surface of the gate insulating film being in contact with the first semiconductor region;
a gate electrode provided on the second surface of the gate insulating film;
a first semiconductor layer of the first conductivity type, provided in the semiconductor substrate;
a third semiconductor region of the second conductivity type, provided in the semiconductor substrate at the second main surface of the semiconductor substrate;
a first electrode provided on the first surface of the first semiconductor region and surfaces of the second semiconductor regions; and
a second electrode provided on a surface of the third semiconductor region, wherein
the first semiconductor layer has a predetermined region, a depth of the predetermined region from the second main surface of the semiconductor substrate is greater than a depth of a region of the first semiconductor layer excluding the predetermined region, from the second main surface of the semiconductor substrate.