US 12,249,505 B2
Semiconductor device including epitaxial region
Gyeom Kim, Hwaseong-si (KR); Dongwoo Kim, Incheon (KR); Jihye Yi, Suwon-si (KR); Jinbum Kim, Seoul (KR); Sangmoon Lee, Suwon-si (KR); and Seunghun Lee, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 17, 2023, as Appl. No. 18/513,297.
Application 18/513,297 is a continuation of application No. 17/853,990, filed on Jun. 30, 2022, granted, now 11,869,765.
Application 17/853,990 is a continuation of application No. 17/006,799, filed on Aug. 29, 2020, granted, now 11,380,541, issued on Jul. 5, 2022.
Claims priority of application No. 10-2019-0148399 (KR), filed on Nov. 19, 2019.
Prior Publication US 2024/0087884 A1, Mar. 14, 2024
Int. Cl. H01L 21/02 (2006.01); B82Y 10/00 (2011.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/485 (2006.01); H01L 23/532 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/161 (2006.01); H01L 29/165 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/02293 (2013.01) [H01L 21/28518 (2013.01); H01L 21/76897 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 23/485 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/41766 (2013.01); H01L 29/41791 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66553 (2013.01); H01L 29/6656 (2013.01); H01L 29/775 (2013.01); H01L 29/7848 (2013.01); H01L 29/78696 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, comprising:
forming an active pattern, wherein the active pattern has a first active portion and a second active portion;
forming an isolation layer on a side surface of a lower region of the active pattern, wherein the isolation layer has a first isolation portion and a second isolation portion;
forming a structure on the first active portion of the active pattern and the first isolation portion of the isolation layer;
forming a source/drain recess region by etching the second active portion of the active pattern using an etching process using the structure as an etch mask;
forming a first epitaxial region in the source/drain recess region;
forming an interlayer insulating layer on the first epitaxial region and the second isolation portion of the isolation layer;
forming a contact hole penetrating through the interlayer insulating layer and exposing the first epitaxial region;
forming an insulating contact spacer on a sidewall of the contact hole;
partially etching the first epitaxial region exposed by the contact hole to form a recessed surface of the first epitaxial region, after forming the insulating contact spacer;
forming a second epitaxial region on the recessed surface of the first epitaxial region; and
forming a contact structure contacting the second epitaxial region,
wherein the second epitaxial region vertically overlaps the insulating contact spacer and the contact structure.