US 12,249,398 B2
Data transmission circuit, data transmission method and storage device
Enpeng Gao, Hefei (CN); Kangling Ji, Hefei (CN); and Zengquan Wu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/757,321
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
PCT Filed Aug. 12, 2021, PCT No. PCT/CN2021/112221
§ 371(c)(1), (2) Date Oct. 6, 2022,
PCT Pub. No. WO2022/205735, PCT Pub. Date Oct. 6, 2022.
Claims priority of application No. 20211033856.0 (CN), filed on Mar. 29, 2021.
Prior Publication US 2024/0185901 A1, Jun. 6, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/22 (2006.01); G06F 3/06 (2006.01)
CPC G11C 7/22 (2013.01) [G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data transmission circuit, comprising:
a controllable delay module, configured to generate a delayed read command in response to a mode register read command; and
a mode register data processing unit, connected to the controllable delay module, and configured to read a setting parameter from a mode register in response to the mode register read command, and to output the setting parameter in response to the delayed read command;
wherein a time difference between a start moment of outputting of the setting parameter and a moment when the controllable delay module receives the mode register read command is a first preset threshold.