US 12,249,396 B2
Folding ordering scheme for improved throughput in non-volatile memory
Abhinandan Venugopal, Bengaluru (IN); and Amit Sharma, Bengaluru (IN)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 3, 2023, as Appl. No. 18/346,329.
Claims priority of provisional application 63/478,209, filed on Jan. 3, 2023.
Prior Publication US 2024/0221802 A1, Jul. 4, 2024
Int. Cl. G11C 7/10 (2006.01)
CPC G11C 7/1096 (2013.01) [G11C 7/1069 (2013.01); G11C 7/1087 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-volatile memory device, comprising:
a plurality of control circuits each configured to connect to a plurality of non-volatile memory cells of a corresponding memory die, each of the control circuits comprising a corresponding plurality of sets of data latches configured to store data to be written to and data read from the non-volatile memory cells of the corresponding memory die, each of the control circuits configured to:
perform a folding operation of pages of host data previously written in binary format in the memory cells of the corresponding memory die to be written in an N bit per cell format in the memory cells of the corresponding memory die, where, to perform the folding operation, each of the control circuits is configured to:
read out and store in the corresponding plurality of sets of data latches N pages of the host data previously written in the binary format in the memory cells of the corresponding memory die; and
write the N pages of the host data previously written in the memory cells of the corresponding memory die in a binary format into memory cells of the corresponding memory die in the N bit per cell format in a two phase programming operation in which the memory cells are programmed into an intermediate set of distributions in an initial programming phase and subsequently programmed into the N bit per cell format in a fine programming phase,
where the plurality of control circuits are configured to perform the folding operation on the plurality of corresponding memory die concurrently, a first sub-set of one or more of the control circuits performing the initial programming phase while a second sub-set of one or more control circuits are performing the fine programming phase.