| CPC G11C 7/109 (2013.01) [G11C 5/063 (2013.01); G11C 7/16 (2013.01)] | 8 Claims |
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1. A memory device comprising:
a memory cell array connected to a first word line, a pair of second word lines, a first operation control line, a second operation control line, a common bit line, and a bit line, and configured to perform a multiply-accumulate (MAC) operation depending on a ternary input provided from the pair of second word lines and a binary weight preset based on the first word line and the bit line;
a peripheral circuit configured to control the memory cell array; and
an ADC (analog-to-digital converter) circuit configured to convert a voltage value dependent on the MAC operation into a digital value,
wherein each memory cell arranged in the memory cell array comprises:
a static random access memory (SRAM) connected to the first word line and the pair of second word lines;
a pair of first transistors connected between the pair of second word lines and a first node, each first transistor having a gate terminal connected to an output terminal of the SRAM;
a second transistor connected between the first node and a second node, and having a gate terminal connected to the first operation control line; and
a third transistor connected between the second node and the common bit line, and having a gate terminal connected to the second operation control line.
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