US 12,249,394 B2
Multi-protocol analog front end circuit
Xiao Yun, Franklin, MA (US); and Vladimir Zlatkovic, Belmont, MA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Oct. 4, 2022, as Appl. No. 17/959,833.
Claims priority of provisional application 63/255,303, filed on Oct. 13, 2021.
Prior Publication US 2023/0111161 A1, Apr. 13, 2023
Int. Cl. G11C 11/4093 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/109 (2013.01) [G11C 5/06 (2013.01); G11C 7/1063 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus for processing an input signal from a memory, the apparatus comprising:
an attenuator circuit comprising (i) a first parallel resistor-capacitor (RC) circuit and (ii) a second parallel RC circuit, wherein the attenuator circuit is configured to attenuate the input signal from the memory to produce an attenuated signal; and
an analog front end (AFE) circuit comprising:
a first amplification stage having an n-type metal-oxide semiconductor (NMOS) transistor, the NMOS transistor having a gate configured to receive the attenuated signal from the attenuator circuit; and
a second amplification stage having a p-type metal-oxide semiconductor (PMOS) transistor, the PMOS transistor having a gate configured to receive the attenuated signal from the attenuator circuit, wherein outputs of the first amplification stage and the second amplification stage are electrically coupled to a common output of the AFE circuit, wherein the first parallel RC circuit is electrically coupled to the gate of the NMOS transistor and the gate of the PMOS transistor, and wherein the second parallel RC circuit is electrically coupled between (i) an electrical ground node and (ii) the gate of the NMOS transistor and the gate of the PMOS transistor.