US 12,249,390 B2
Memory systems with vertical integration
Chieh Lee, Hsinchu (TW); Yi-Ching Liu, Hsinchu (TW); Chia-En Huang, Xinfeng Township (TW); Jen-Yuan Chang, Hsinchu (TW); and Yih Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 12, 2023, as Appl. No. 18/316,743.
Application 18/316,743 is a continuation of application No. 17/461,332, filed on Aug. 30, 2021, granted, now 11,676,641.
Prior Publication US 2023/0282247 A1, Sep. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 5/06 (2006.01); G11C 5/02 (2006.01); H01L 23/48 (2006.01); H10B 12/00 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01); H10N 70/00 (2023.01)
CPC G11C 5/06 (2013.01) [G11C 5/025 (2013.01); H01L 23/481 (2013.01); H10B 12/00 (2023.02); H10B 61/00 (2023.02); H10B 63/84 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02); H10N 70/011 (2023.02); H10N 70/821 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a peripheral layer including a plurality of peripheral circuits;
a plurality of memory array layers disposed with respect to the peripheral layer in a vertical direction, each of the plurality of memory array layers corresponding to one of the plurality of peripheral circuits and including a respective memory array, a respective row decoder circuit, and a respective column sensing circuit; and
a plurality of interconnect structures fully extending across the peripheral layer and the memory array layers along the vertical direction, wherein at least a first one of the plurality of interconnect structures operatively couples the peripheral layer to a first one of the memory array layers but is operatively isolated from a second one of the memory array layers.