US 12,249,389 B2
Memory system and method
Motoki Shimizu, Yokohama Kanagawa (JP); Kenji Sakurada, Yamato Kanagawa (JP); and Naoto Kumano, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Aug. 26, 2022, as Appl. No. 17/896,887.
Claims priority of application No. 2022-043995 (JP), filed on Mar. 18, 2022.
Prior Publication US 2023/0298685 A1, Sep. 21, 2023
Int. Cl. G11C 29/52 (2006.01); G11C 8/08 (2006.01); G11C 29/02 (2006.01); H03M 13/11 (2006.01)
CPC G11C 29/52 (2013.01) [G11C 8/08 (2013.01); G11C 29/021 (2013.01); H03M 13/1125 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a semiconductor memory device including a plurality of memory cells each configured to store data in a non-volatile manner according to a threshold voltage thereof and connected to a word line; and
a controller configured to:
perform an error correction based on hard bit data and soft bit data read from the plurality of memory cells;
generate a first table based on data corrected by the error correction;
determine a voltage difference between a first voltage and a second voltage, the first voltage being a voltage applied to the word line when the data that has been corrected is read; and
correct the generated first table based on the voltage difference.