| CPC G11C 29/42 (2013.01) [G11C 7/1039 (2013.01); G11C 29/1201 (2013.01); G11C 29/702 (2013.01)] | 9 Claims |
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1. A memory system, comprising:
a memory; and
a memory controller which includes a spare buffer suitable for storing an error location in the memory and data at the location, and commands the memory to perform a spare read operation when an address of a region where a read operation needs to be performed matches with an error address stored in the spare buffer, otherwise, commands the memory to perform a normal read operation,
wherein the error address is an address of the region of the memory including the error location,
wherein the memory includes:
a memory core;
a data replacing circuit suitable for generating new read data by replacing a portion of data read from the memory core with a predetermined pattern of data during the spare read operation;
an error correction circuit suitable for detecting an error in the new read data based on an error correction code read from the memory core during the spare read operation, and correcting the error when an error is detected; and
a data transferring circuit suitable for transferring output data of the error correction circuit to the memory controller during the spare read operation, and
wherein when a write operation is required for the region of the memory including the error location,
the memory controller commands the memory to perform a spare write operation and stores a portion of write data in the spare buffer.
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