US 12,249,384 B2
Memory repair circuit, a memory repair method, and a memory device
Hyunseok Kim, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 14, 2023, as Appl. No. 18/368,086.
Claims priority of application No. 10-2023-0015034 (KR), filed on Feb. 3, 2023.
Prior Publication US 2024/0265987 A1, Aug. 8, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/12 (2013.01) [G06F 3/0614 (2013.01); G06F 3/0653 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory repair circuit of a memory module including a plurality of memory packages, the memory repair circuit comprising:
a test circuit configured to test the plurality of memory packages to obtain fail information in each of the plurality of memory packages; and
a redundancy analysis circuit configured to:
obtain a redundant address count in each of the plurality of memory packages,
determine a repair order of the plurality of memory packages based on the fail information and the redundant address count, the fail information including a first fail address in each of the plurality of memory packages and a fail bit count in the first fail address; and
perform a virtual repair on the plurality of memory packages in the repair order and determine a second fail address to be repaired in each of the plurality of memory packages.