US 12,249,383 B2
Shift register and driving method therefor, gate driving circuit, and display device
Wei Yan, Beijing (CN); Zhen Wang, Beijing (CN); Wenwen Qin, Beijing (CN); Han Zhang, Beijing (CN); Deshuai Wang, Beijing (CN); Jian Zhang, Beijing (CN); Yue Shan, Beijing (CN); Xiaoyan Yang, Beijing (CN); Yadong Zhang, Beijing (CN); and Jian Sun, Beijing (CN)
Assigned to BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/794,991
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Sep. 28, 2021, PCT No. PCT/CN2021/121419
§ 371(c)(1), (2) Date Jul. 25, 2022,
PCT Pub. No. WO2023/050086, PCT Pub. Date Apr. 6, 2023.
Prior Publication US 2024/0212772 A1, Jun. 27, 2024
Int. Cl. G11C 19/28 (2006.01); G09G 3/20 (2006.01)
CPC G11C 19/28 (2013.01) [G09G 3/20 (2013.01); G09G 2310/0286 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A shift register, comprising a pull-up control sub-circuit, a pull-down control sub-circuit, an output sub-circuit and a noise reduction sub-circuit;
wherein the pull-up control sub-circuit is electrically connected with a first input terminal, a second output terminal, a first signal terminal, a second signal terminal and a pull-up control node, respectively, and is configured to provide a signal of the first signal terminal or the second signal terminal to the pull-up control node under control of the first input terminal and the second output terminal;
the pull-down control sub-circuit is electrically connected with a first clock signal terminal, a second clock signal terminal, the first signal terminal, the second signal terminal, the pull-up control node, a pull-down node, a first power supply terminal and a second power supply terminal, respectively, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, the first clock signal terminal and the second clock signal terminal;
the output sub-circuit is electrically connected with the pull-up control node, the first power supply terminal, a third clock signal terminal, a first output terminal, a fourth clock signal terminal and the second output terminal, respectively, and is configured to provide a signal of the third clock signal terminal to the first output terminal and provide a signal of the fourth clock signal terminal to the second output terminal under control of the pull-up control node and the first power supply terminal; and
the noise reduction sub-circuit is electrically connected with the pull-up control node, the first output terminal, the second output terminal, the pull-down node and the second power supply terminal, respectively, and is configured to provide a signal of the second power supply terminal to the pull-up control node, the first output terminal and the second output terminal under control of the pull-down node.