US 12,249,382 B2
Reading circuit for differential OTP memory
Xuecheng Man, Beijing (CN); and Xuan Ma, Beijing (CN)
Assigned to SG MICRO CORP, Beijing (CN)
Appl. No. 18/257,946
Filed by SG MICRO CORP, Beijing (CN)
PCT Filed Oct. 21, 2021, PCT No. PCT/CN2021/125343
§ 371(c)(1), (2) Date Jun. 16, 2023,
PCT Pub. No. WO2022/127361, PCT Pub. Date Jun. 23, 2022.
Claims priority of application No. 202011508418.5 (CN), filed on Dec. 18, 2020.
Prior Publication US 2024/0105274 A1, Mar. 28, 2024
Int. Cl. G11C 17/18 (2006.01); G11C 17/16 (2006.01)
CPC G11C 17/18 (2013.01) [G11C 17/16 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A reading circuit for a differential one time programmable (OTP) memory which comprises a first memory cell and a second memory cell in a differentially symmetrical structure, wherein the reading circuit is connected between the first memory cell and the second memory cell and comprises:
a detector having a first input connected to the first memory cell and a second input connected to the second memory cell, configured to detect one of a resistance value of a first fuse of the first memory cell, a resistance value of a second fuse of the second memory cell and a resistance difference between the first fuse and the second fuse after a burn-in operation of the first memory or the second memory is completed; and
a latch connected to the detector, configured to provide a readout data according to one of the resistance value of the first fuse, the resistance value of the second fuse and the resistance difference between the first fuse and the second fuse detected by the detector.