US 12,249,381 B2
Faster multi-cell read operation using reverse read calibrations
Go Shikata, San Jose, CA (US); and Kitae Park, Cupertino, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 3, 2023, as Appl. No. 18/117,268.
Claims priority of provisional application 63/322,818, filed on Mar. 23, 2022.
Prior Publication US 2023/0326532 A1, Oct. 12, 2023
Int. Cl. G11C 16/26 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/08 (2013.01); G11C 16/24 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and
control logic coupled with the memory array, the control logic to perform operations comprising:
determining a metadata value characterizing a first read level voltage of a highest threshold voltage distribution of a subset of the plurality of memory cells, wherein the metadata value comprises at least one of a failed byte count or a failed bit count;
adjusting, based on the metadata value, a second read level voltage for a second-highest threshold voltage distribution of the subset of the plurality of memory cells; and
causing, to perform an initial calibrated read of the subset of the plurality of memory cells, the adjusted second read level voltage to be applied to a wordline of the plurality of wordlines to read the second-highest threshold voltage distribution.