US 12,249,380 B2
Semiconductor memory device with voltages applied to global drain select lines and method of operating the semiconductor memory device
Hee Youl Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Dec. 8, 2022, as Appl. No. 18/077,572.
Claims priority of application No. 10-2022-0085352 (KR), filed on Jul. 12, 2022.
Prior Publication US 2024/0021248 A1, Jan. 18, 2024
Int. Cl. G11C 16/14 (2006.01); G11C 16/04 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/14 (2013.01) [G11C 16/0483 (2013.01); G11C 16/32 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a memory block including a plurality of memory cell strings;
a voltage supply circuit configured to apply operating voltages to global drain select lines, global source select lines, and global word lines, and to apply an erase voltage to bit lines of the memory block or to the bit lines and a source line of the memory block during an erase operation;
a pass circuit configured to couple the global drain select lines, the global source select lines, and the global word lines to local drain select lines, local source select lines, and local word lines, respectively, in response to a block select signal; and
control logic configured to control the voltage supply circuit to apply a first operating voltage to the global drain select lines and thereafter apply a second operating voltage, having a potential higher than a potential of the block select signal, to the global drain select lines,
wherein the voltage supply circuit applies the second operating voltage to a first global drain select line, among the global drain select lines, and applies the second operating voltage to a second global drain select line, among the global drain select lines, after a certain time has elapsed.