US 12,249,378 B2
CELSRC voltage separation between SLC and XLC for SLC program average ICC reduction
Yu-Chung Lien, San Jose, CA (US); Deepanshu Dutta, Fremont, CA (US); Sarath Puthenthermadam, San Jose, CA (US); and Jiahui Yuan, Fremont, CA (US)
Assigned to SanDisk Technologies LLC
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Feb. 8, 2022, as Appl. No. 17/666,810.
Prior Publication US 2023/0253049 A1, Aug. 10, 2023
Int. Cl. G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/3459 (2013.01); G11C 2211/5621 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-volatile semiconductor memory device, comprising:
a bit line;
a source line;
a memory string comprising a plurality of memory cells connected in series between the source line and the bit line; and
control circuitry coupled to the plurality of memory cells, the source line, and the bit line, wherein the control circuitry is configured to:
determine if a program operation is a single-bit program operation or multi-bit program operation;
in response to the determination, identify a voltage level to set the source line to during a programming pulse of each program loop of the program operation; and
perform the program operation on the memory string, the program operation including setting the source line to the voltage level.