| CPC G11C 16/08 (2013.01) [G11C 16/0483 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01)] | 19 Claims |
|
19. A storage device comprising:
a plurality of memory cells provided in a plurality of channel holes extending through a plurality of word-lines stacked on substrate, wherein the plurality memory cells are coupled to a word-line from among the plurality of word-lines; and
a word-line cut region dividing the plurality of word-lines into a plurality of memory blocks; and
an error correction code (ECC) decoder configured to:
obtain a first bit read from a first memory cell and a second bit read from a second memory cell during a read operation on the plurality of memory cells, and
perform ECC decoding on an ECC sector corresponding to the first memory cell and the second memory cell by applying a first log likelihood ratio (LLR) value to the first bit and a second LLR value to the second bit, wherein the first LLR value is different from the second LLR value,
wherein the first LLR value is determined based on a distance between the first memory cell and the word-line cut region, and the second LLR value is determined based on a distance between the second memory cell and the word-line cut region.
|