| CPC G11C 16/0433 (2013.01) [G11C 16/20 (2013.01); G11C 16/24 (2013.01); G11C 16/30 (2013.01)] | 27 Claims |
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1. A memory device, comprising:
a string including select transistors and memory cells coupled in series between a bit line and a source line;
a voltage generation circuit configured to:
provide a turn-on voltage or a turn-off voltage to select lines coupled to the select transistors; and
provide at least one operating voltage to word lines coupled to the memory cells, or discharge the select lines or the word lines;
a page buffer configured to precharge or discharge the bit line, wherein when the select transistors are turned off in response to the turn-off voltage, the page buffer discharges the bit line; and
a channel initializing circuit configured to control the voltage generation circuit and the page buffer to initialize a channel of the string when an operation performed on the memory cells is completed or is suspended before being completed.
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