US 12,249,372 B2
Encoding additional states in a three-dimensional crosspoint memory architecture
Rouhollah Mousavi Iraei, Albuquerque, NM (US); Kiran Pangal, Fremont, CA (US); Saad P. Monasa, Sacramento, CA (US); Mini Goel, Milpitas, CA (US); Raymond Zeng, Cupertino, CA (US); and Hemant P. Rao, Albuquerque, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 20, 2021, as Appl. No. 17/408,352.
Prior Publication US 2023/0064007 A1, Mar. 2, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01)
CPC G11C 13/0069 (2013.01) [G11C 13/0004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/004 (2013.01); G11C 2013/0078 (2013.01); H10B 63/84 (2023.02)] 25 Claims
OG exemplary drawing
 
1. A non-volatile memory device comprising:
a memory array comprising:
a plurality of non-volatile memory cells, each memory cell comprising a phase change material (PM) region and a select device (SD) region in series with the PM region; and
address lines to apply voltages across the memory cells;
memory controller circuitry to interface with the address lines of the memory cells, the memory controller circuitry to encode a state in a memory cell by:
applying a first voltage across a set of address lines over a first time period to cause a first current to flow in the memory cell, wherein the first current applied over the first time period causes the PM region of the memory cell to be placed into an amorphous state and the SD region of the memory cell to be placed into an amorphous state; and
applying a second voltage across the set of address lines over a second time period after the first time period to cause a second current to flow in the memory cell, wherein the second current applied over the second time period causes the SD region of the memory cell to be placed into a crystalline state and the PM region of the memory cell to remain in the amorphous state.