US 12,249,371 B2
Reconfigurable in-memory physically unclonable function
Yun-Feng Kao, Hsinchu (TW); and Katherine H. Chiang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jan. 14, 2022, as Appl. No. 17/576,906.
Claims priority of provisional application 63/260,192, filed on Aug. 12, 2021.
Prior Publication US 2023/0046138 A1, Feb. 16, 2023
Int. Cl. G11C 11/00 (2006.01); G11C 11/16 (2006.01); G11C 11/22 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/0059 (2013.01) [G11C 11/1695 (2013.01); G11C 11/2295 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A physically unclonable function (PUF) device, comprising: first and second inverters, each of the first and second inverters comprising: a common gate node; and a common drain node, wherein the common drain node of the first inverter is electrically connected to the common gate node of the second inverter, and wherein the first and second inverters are connected in series between the common gate node of the first inverter and the common drain node of the second inverter and configure to induce a voltage change at the common drain node of the second inverter by a voltage change at the common gate node of the first inverter through a voltage change at the common drain node of the first inverter; a common output node; a first resistive memory device (RMD) electrically connected directly to the common drain node of the first inverter and directly to the common output node; and a second RMD electrically connected directly to the common drain node of the second inverter and directly to the common output node, wherein the first inverter is configured to receive a programming voltage and the common output node is configured to float in a randomized programming operation.