US 12,249,370 B2
Systems and techniques for accessing multiple memory cells concurrently
Federico Pio, Brugherio (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 9, 2023, as Appl. No. 18/208,103.
Application 18/208,103 is a division of application No. 17/733,683, filed on Apr. 29, 2022, granted, now 11,705,194.
Application 17/733,683 is a division of application No. 16/712,682, filed on Dec. 12, 2019, granted, now 11,335,402, issued on May 17, 2022.
Claims priority of provisional application 62/782,015, filed on Dec. 19, 2018.
Prior Publication US 2024/0013833 A1, Jan. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/003 (2013.01) [G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0061 (2013.01); G11C 13/0069 (2013.01); G11C 2013/0045 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A method, comprising:
identifying a first memory cell of a first section of a memory tile to be read, wherein memory cells in the first section of the memory tile are configured to be read in response to application of a first read pulse having a first polarity, wherein the memory tile includes more than one deck of memory cells;
identifying a second memory cell of a second section of the memory tile to read, wherein memory cells in the second section of the memory tile are configured to be read in response to application of a second read pulse having a second polarity different than the first polarity;
reading the first memory cell; and
reading the second memory cell concurrently with reading the first memory cell based at least in part on identifying the first memory cell of the first section and the second memory cell of the second section.