US 12,249,367 B2
Write assist circuit for memory device
Chia-Che Chung, Hsinchu (TW); Hsin-Cheng Lin, Taipei (TW); and Chee-Wee Liu, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and NATIONAL TAIWAN UNIVERSITY, Taipei (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and NATIONAL TAIWAN UNIVERSITY, Taipei (TW)
Filed on Apr. 13, 2022, as Appl. No. 17/720,154.
Prior Publication US 2023/0335186 A1, Oct. 19, 2023
Int. Cl. G11C 11/00 (2006.01); G11C 11/419 (2006.01)
CPC G11C 11/419 (2013.01) 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a memory cell configured to operate with a first supply voltage and a second supply voltage different from the first supply voltage; and
a first write assist circuit comprising a first write assist switch and a second write assist switch that are coupled to the memory cell through a first data line, wherein in a write operation of a data, having a first logic value, to the memory cell,
the first write assist switch is configured to transmit the first supply voltage to the first data line in response to a first control signal, received at a control terminal of the first write assist switch and having a voltage level of the second supply voltage, when the second write assist switch is configured to be turned off in response to a second control signal,
wherein in a read operation of the data the second control signal is floating.