| CPC G11C 11/4097 (2013.01) [G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); H10B 12/20 (2023.02)] | 13 Claims |
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1. A semiconductor-element-including memory device that is a memory device in which in plan view on a substrate, a plurality of pages are arranged in a column direction, each of the pages being constituted by a plurality of memory cells arranged in a row direction,
each memory cell included in each of the pages comprising:
a semiconductor body that stands on the substrate in a vertical direction relative to the substrate or that extends along the substrate in a horizontal direction relative to the substrate;
a first impurity region and a second impurity region that are disposed at respective ends of the semiconductor body;
a gate insulator layer that partially or entirely surrounds a side surface of the semiconductor body; and
a first gate conductor layer and a second gate conductor layer that cover the gate insulator layer and that are disposed adjacent to each other, wherein
voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region are controlled to retain a group of positive holes, generated by an impact ionization phenomenon, inside the semiconductor body,
in a page write operation, a voltage of the semiconductor body is made equal to a first data retention voltage that is higher than the voltage of one of the first impurity region or the second impurity region or that is higher than the voltages of both of the first impurity region and the second impurity region,
in a page erase operation, the group of positive holes in the semiconductor body are made to be extinct by controlling the voltages applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer, and the voltage of the semiconductor body is made equal to a second data retention voltage that is lower than the first data retention voltage,
the first impurity region of each memory cell is connected to a source line, the second impurity region thereof is connected to a corresponding one of bit lines, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a corresponding one of word lines, and the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a corresponding one of plate lines, and
in the page erase operation, a positive voltage pulse is applied to one or both of the word line and the plate line of a page, among the pages, for which selective erasing is performed, a ground voltage is applied to the word line and the plate line of a non-selected page among the pages, and the ground voltage is applied to all of the source line and the bit lines.
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