US 12,249,365 B2
Memory device capable of performing in-memory computing
Shu-Sen Lin, Hsinchu County (TW)
Assigned to WINDBOND ELECTRONICS CORP., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Mar. 6, 2023, as Appl. No. 18/178,958.
Prior Publication US 2024/0304232 A1, Sep. 12, 2024
Int. Cl. G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01); H03K 19/20 (2006.01)
CPC G11C 11/4087 (2013.01) [G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); H03K 19/20 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device capable of performing in-memory computing, comprising:
a memory cell array comprising a plurality of memory cells arranged in a two-dimensional array, wherein the memory cells on each row of the memory cell array are connected to a corresponding word line, and the memory cells on each column of the memory cell array are connected to a corresponding bit line;
a sense amplifier detecting a voltage level of the activated bit line and a voltage level of an inverse bit line corresponding to the bit line;
a voltage control circuit selecting a detection voltage provided to the sense amplifier according to a control signal from a memory controller; and
a word line decoding circuit activating a first word line and a second word line among the word lines according to the control signal,
wherein:
the control signal comprises a normal read control signal, an OR operation control signal, and an AND operation control signal, and
the normal read control signal, the OR operation control signal, or the AND operation control signal is in a high logic state.