US 12,249,364 B2
Apparatus with non-linear delay variations for scheduling memory refresh operations and methods for operating the same
Huai-Yuan Tseng, San Ramon, CA (US); Akira Goda, Tokyo (JP); Kishore Kumar Muchherla, Fremont, CA (US); James Fitzpatrick, Laguna Niguel, CA (US); Tomoharu Tanaka, Yokohama (JP); Eric N. Lee, San Jose, CA (US); Dung V. Nguyen, San Jose, CA (US); and David Ebsen, Minnetonka, MN (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 17, 2022, as Appl. No. 17/890,040.
Prior Publication US 2024/0062799 A1, Feb. 22, 2024
Int. Cl. G11C 11/406 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/40615 (2013.01) [G11C 11/40618 (2013.01); G11C 11/4076 (2013.01); G11C 11/4085 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory array including rewritable memory cells configured to store charges representative of stored data; and
a memory controller operably coupled to the memory array and configured to:
perform an initial implementation of a touch up operation to restore the stored charges to offset or reverse charge loss and maintain the stored data; and
determine a schedule for performing subsequent implementations of the touch up operation, wherein the schedule includes different delays between successive implementations of the touch up operation, wherein the different delays follow a predetermined increasing non-linear pattern.