US 12,249,362 B2
Single plate configuration and memory array operation
Ferdinando Bedeschi, Biassono (IT); and Efrem Bolandrina, Fiorano Al Serio (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 10, 2023, as Appl. No. 18/120,133.
Application 18/120,133 is a division of application No. 16/983,469, filed on Aug. 3, 2020, granted, now 11,626,151.
Application 16/983,469 is a continuation of application No. 15/845,893, filed on Dec. 18, 2017, granted, now 10,762,944, issued on Sep. 1, 2020.
Prior Publication US 2023/0206977 A1, Jun. 29, 2023
Int. Cl. G11C 11/22 (2006.01); G06F 13/16 (2006.01)
CPC G11C 11/2259 (2013.01) [G06F 13/1694 (2013.01); G11C 11/221 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
setting a first voltage of a plate that is coupled with a first memory cell and a second memory cell, wherein the first memory cell is coupled with a first digit line;
isolating the first digit line from a second digit line that is coupled with the second memory cell based at least in part on setting the first voltage of the plate;
coupling the plate with the second digit line, wherein the first voltage is applied to the second digit line based at least in part on the coupling and is not applied to the first digit line based at least in part on the isolating; and
applying, based at least in part on coupling the plate with the second digit line and isolating the first digit line from the second digit line, a second voltage to a word line that is coupled with the first memory cell and the second memory cell, and a third voltage to the first digit line.