US 12,249,283 B2
Display apparatus
Kazuyoshi Omata, Tokyo (JP); Hiroyuki Kimura, Tokyo (JP); Makoto Shibusawa, Tokyo (JP); and Hiroshi Tabatake, Tokyo (JP)
Assigned to Japan Display Inc., Tokyo (JP)
Filed by Japan Display Inc., Tokyo (JP)
Filed on Jan. 9, 2024, as Appl. No. 18/407,529.
Application 18/407,529 is a continuation of application No. 18/148,002, filed on Dec. 29, 2022, granted, now 11,908,409.
Application 18/148,002 is a continuation of application No. 17/315,771, filed on May 10, 2021, granted, now 11,568,810, issued on Jan. 31, 2023.
Application 17/315,771 is a continuation of application No. 16/784,693, filed on Feb. 7, 2020, granted, now 11,004,394, issued on May 11, 2021.
Application 16/784,693 is a continuation of application No. 16/119,655, filed on Aug. 31, 2018, granted, now 10,573,239, issued on Feb. 25, 2020.
Application 16/119,655 is a continuation of application No. 15/365,428, filed on Nov. 30, 2016, granted, now 10,096,283, issued on Oct. 9, 2018.
Application 15/365,428 is a continuation of application No. 15/167,401, filed on May 27, 2016, granted, now 9,542,888, issued on Jan. 10, 2017.
Application 15/167,401 is a continuation of application No. 14/056,282, filed on Oct. 17, 2013, granted, now 9,368,058, issued on Jun. 14, 2016.
Claims priority of application No. 2012-231740 (JP), filed on Oct. 19, 2012; application No. 2013-012286 (JP), filed on Jan. 25, 2013; and application No. 2013-032359 (JP), filed on Feb. 21, 2013.
Prior Publication US 2024/0144882 A1, May 2, 2024
Int. Cl. G09G 3/3233 (2016.01); G09G 3/32 (2016.01); G09G 3/3258 (2016.01); H05B 45/60 (2022.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01); G09G 3/20 (2006.01); G09G 3/325 (2016.01); H01L 27/12 (2006.01); H10K 59/123 (2023.01); H10K 59/35 (2023.01)
CPC G09G 3/3233 (2013.01) [G09G 3/32 (2013.01); G09G 3/3258 (2013.01); H05B 45/60 (2020.01); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/131 (2023.02); G09G 3/2003 (2013.01); G09G 3/325 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0452 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0262 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0252 (2013.01); G09G 2320/043 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H10K 59/123 (2023.02); H10K 59/351 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A display device including a plurality of pixels, the display device comprising:
a semiconductor layer;
a first insulation layer on the semiconductor layer;
a first conductive layer on the first insulation layer;
a second insulation layer on the first insulation layer and the first conductive layer;
a second conductive layer on the second insulation layer;
a third insulation layer on the second insulation layer and the second conductive layer;
a third conductive layer on the third insulation layer; and
a partition insulation layer on the third insulation layer and the third conductive layer, wherein
each of the plurality of pixels includes a display element, a drive transistor, a first conductor, a second conductor, and an output switch, the display element including electrodes,
one of the electrodes of the display element is formed in the third conductive layer,
a channel of the drive transistor is formed in the semiconductor layer,
a gate of the drive transistor is formed in the first conductive layer,
the second conductive layer extends so as not to contact the gate, and not to contact a source or a drain of the drive transistor,
the one of the electrodes of the display element, the second conductive layer, and the gate of the drive transistor overlap with each other in a plane view,
the partition insulation layer covers an edge of the one of the electrodes of the display element,
the partition insulation layer includes an opening exposing a part of an upper surface of the one of electrodes of the display element,
another one of the electrodes of the display element is electrically connected to the second conductor,
the one of the electrodes of the display element is electrically connected to one of the source and the drain of the drive transistor,
one of a source and a drain of the output switch is electrically connected to the first conductor,
another one of the source and the drain of the output switch is electrically connected to the another one of the source and the drain of the drive transistor,
the first conductor is electrically connected to a high potential power line,
the second conductor is electrically connected to a low potential power line,
the drive transistor is configured to control a current value from the first conductor to the display element,
the output switch is configured to select to supply or not to supply a current from the first conductor to the display element, and
the output switch is configured to be controlled by a signal different from that of the drive transistor.