US 12,249,268 B2
Pixel and display device including the same
Sunkwang Kim, Seoul (KR); and Kangmoon Jo, Hwaseong-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by Samsung Display Co., Ltd., Yongin-Si (KR)
Filed on Aug. 30, 2022, as Appl. No. 17/899,382.
Claims priority of application No. 10-2021-0174038 (KR), filed on Dec. 7, 2021.
Prior Publication US 2023/0178004 A1, Jun. 8, 2023
Int. Cl. G09G 3/32 (2016.01); G09G 3/3233 (2016.01); H01L 25/075 (2006.01); H01L 33/50 (2010.01); H01L 33/54 (2010.01); H01L 33/62 (2010.01)
CPC G09G 3/32 (2013.01) [G09G 3/3233 (2013.01); H01L 25/0753 (2013.01); H01L 33/505 (2013.01); H01L 33/54 (2013.01); H01L 33/62 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0275 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A pixel comprising:
first to fourth driving transistors;
a first switching transistor including a first active pattern and electrically connected to the first driving transistor;
a second switching transistor including a second active pattern and electrically connected to the second driving transistor;
a first light emitting diode connected to the first driving transistor;
a second light emitting diode connected to the second driving transistor and spaced apart from the first light emitting diode in a first direction when viewed in a plan view;
a third light emitting diode connected to the third driving transistor and disposed between the first light emitting diode and the second light emitting diode when viewed in a plan view; and
a fourth light emitting diode connected to the fourth driving transistor and disposed between the first light emitting diode and the second light emitting diode when viewed in a plan view,
wherein a planar area of the first driving transistor is smaller than a planar area of each of the third driving transistor and the fourth driving transistor, a planar area of the second driving transistor is smaller than the planar area of the each of the third driving transistor and the fourth driving transistor, a first data signal is applied to the first driving transistor and the second driving transistor, a second data signal different from the first data signal is applied to the third driving transistor, and a third data signal different from the first data signal and the second data signal is applied to the fourth driving transistor, and
wherein the first switching transistor and the second switching transistor are connected to a same gate pattern to which a scan signal is applied.