US 12,249,017 B2
Reduced display processing unit transfer time to compensate for delayed graphics processing unit render time
Yongjun Xu, Beijing (CN); Nan Zhang, Beijing (CN); Wenkai Yao, Beijing (CN); and Long Han, Shanghai (CN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Appl. No. 17/794,876
Filed by QUALCOMM Incorporated, San Diego, CA (US)
PCT Filed Feb. 21, 2020, PCT No. PCT/CN2020/076205
§ 371(c)(1), (2) Date Jul. 22, 2022,
PCT Pub. No. WO2021/164004, PCT Pub. Date Aug. 26, 2021.
Prior Publication US 2023/0073736 A1, Mar. 9, 2023
Int. Cl. G06T 15/00 (2011.01); G06F 1/12 (2006.01); G06T 1/20 (2006.01)
CPC G06T 15/005 (2013.01) [G06F 1/12 (2013.01); G06T 1/20 (2013.01)] 16 Claims
OG exemplary drawing
 
7. An apparatus for frame processing, comprising:
a memory; and
at least one processor coupled to the memory and configured to:
determine whether a first frame is currently transferring or has been transferred after completion of a rendering of a second frame, the second frame following the first frame;
use, with at least one clock, a first set of clock speeds when the first frame is determined to be currently transferring and a second set of clock speeds when the first frame is determined to have been transferred, the second set of clock speeds being faster than the first set of clock speeds;
transfer the second frame based on the used set of clock speeds after completion of the transfer of the first frame
extend a vertical synchronization (VSYNC) period from a first period T to a second period T+a when the first frame has already been transferred, wherein the at least one clock is used with the second set of clock speeds; and
determine the second set of clock speeds based on reducing a transfer completion time of the second frame in order to provide a transfer of the second frame within a third period T−a.