US 12,248,869 B2
Three dimensional circuit implementing machine trained network
Steven L. Teig, Menlo Park, CA (US); and Kenneth Duong, San Jose, CA (US)
Assigned to Adeia Semiconductor Inc., San Jose, CA (US)
Filed by Adeia Semiconductor Inc., San Jose, CA (US)
Filed on Sep. 19, 2023, as Appl. No. 18/469,910.
Application 18/469,910 is a continuation of application No. 17/500,374, filed on Oct. 13, 2021, granted, now 11,790,219.
Application 17/500,374 is a continuation of application No. 15/859,551, filed on Dec. 31, 2017, granted, now 11,176,450, issued on Nov. 16, 2021.
Claims priority of provisional application 62/541,064, filed on Aug. 3, 2017.
Prior Publication US 2024/0152743 A1, May 9, 2024
Int. Cl. G06N 3/065 (2023.01); G06F 11/14 (2006.01); G06F 11/20 (2006.01); G06N 3/04 (2023.01); G06N 3/048 (2023.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01); G06N 3/082 (2023.01); G06N 3/084 (2023.01); H01L 23/31 (2006.01); H01L 25/04 (2023.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01); H01L 25/075 (2006.01); H01L 25/11 (2006.01); H03K 19/21 (2006.01)
CPC G06N 3/065 (2023.01) [G06F 11/1423 (2013.01); G06F 11/2007 (2013.01); G06F 11/2028 (2013.01); G06F 11/2041 (2013.01); G06F 11/2051 (2013.01); G06N 3/04 (2013.01); G06N 3/048 (2023.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01); G06N 3/082 (2013.01); G06N 3/084 (2013.01); H01L 23/3128 (2013.01); H01L 25/0657 (2013.01); G06F 2201/85 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 25/043 (2013.01); H01L 25/074 (2013.01); H01L 25/0756 (2013.01); H01L 25/117 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17181 (2013.01); H01L 2225/06503 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06582 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/16235 (2013.01); H03K 19/21 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device comprising:
a first IC layer comprising a plurality of first computational units serving as neurons of a first neural layer of a neural network to receive first input and generate first output; and
a second IC layer comprising a plurality of second computational units serving as neurons of a second neural layer of the neural network and interconnected with the first computational units, the second computational units to receive as second input the first output from the first neural layer and to generate second output,
wherein the first IC layer and second IC layer are vertically stacked and bonded to each other.