CPC G06N 3/063 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 7/50 (2013.01); G06F 18/2193 (2023.01); G06N 3/04 (2013.01); G06V 10/95 (2022.01); G06V 10/955 (2022.01)] | 20 Claims |
1. A data processing device comprising:
a processor; and
a first memory storing instructions that, when executed by the processor, cause the processor to:
determine whether or not each of binarized input data is a predetermined value;
store, in a second memory, a plurality of coefficients and coefficient address information including information related to coefficient addresses where the plurality of coefficients are stored;
read the coefficient address from the second memory based on a determination result of the binarized input data being the predetermined value or not and read the coefficient from the second memory based on the coefficient address; and
execute an arithmetic operation related to the acquired coefficient.
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