US 12,248,859 B2
Integrated circuit defect diagnosis using machine learning
Ronald D. Blanton, Pittsburgh, PA (US); and Soumya Mittal, Pittsburgh, PA (US)
Assigned to Carnegie Mellon University, Pittsburgh, PA (US)
Filed by Carnegie Mellon University, Pittsburgh, PA (US)
Filed on Aug. 6, 2020, as Appl. No. 16/986,963.
Claims priority of provisional application 62/922,401, filed on Aug. 7, 2019.
Prior Publication US 2021/0042644 A1, Feb. 11, 2021
Int. Cl. G06N 20/20 (2019.01); G06F 11/07 (2006.01); G06N 3/06 (2006.01); G06N 5/04 (2023.01); G06N 20/00 (2019.01)
CPC G06N 20/20 (2019.01) [G06F 11/0751 (2013.01); G06F 11/0766 (2013.01); G06N 3/06 (2013.01); G06N 5/04 (2013.01); G06N 20/00 (2019.01)] 10 Claims
OG exemplary drawing
 
1. A method comprising:
applying one or more patterns to the circuit;
identifying one or more failing patterns of a circuit as patterns that cause failing outputs from the circuit;
tracing failing outputs of the circuit to one or more candidate defect locations in the circuit;
classifying each failing pattern as a type-1 pattern, indicating that the failing pattern is explained by a single fault, a type-2 pattern, wherein the failing pattern is explained by multiple faults, or a type-3 pattern, wherein the failing pattern is not explained, indicating interacting defects are present in the circuit, the classifying comprising:
identifying one or more covers comprising a set of the candidate defect locations in the circuit that collectively explain all failing patterns;
assigning a fault type to each candidate defect location, the fault type selected from a group consisting of STUCK, CELL, BRIDGE and OPEN;
extracting, for a supervised machine learning model, a set of features from each candidate defect location based on patterns predicted by stuck-at and X-fault simulations of the candidate defect locations compared to observed failing patterns;
for each type-3 pattern:
applying a defect-level, fault type-specific machine learning model for each fault type to each candidate defect location, each fault type-specific machine learning model taking as input the features extracted from the candidate defect location and outputting a probability that the candidate defect location is the fault type which the fault type-specific machine learning model has been trained to detect; and
applying a cover-level machine learning model when the probability produced by at least one of the fault type-specific machine learning models returns a probability exceeding a predetermined threshold for at least one of the candidate defect locations in the cover, to classify the set of candidate defects in the cover as being correct or incorrect;
wherein a correct output from the cover-level machine learning model indicates that the cover represents actual defects in the circuit.