US 12,248,848 B2
Scalable gate control in quantum circuit assemblies
Sushil Subramanian, Hillsboro, OR (US); Stefano Pellerano, Beaverton, OR (US); Ravi Pillarisetty, Portland, OR (US); Jong Seok Park, Hillsboro, OR (US); and Todor M. Mladenov, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 7, 2021, as Appl. No. 17/340,173.
Prior Publication US 2022/0391738 A1, Dec. 8, 2022
Int. Cl. G06N 10/00 (2022.01); H03M 1/66 (2006.01)
CPC G06N 10/00 (2019.01) [H03M 1/66 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A quantum circuit assembly, comprising:
a signal path, comprising a first capacitor and a second capacitor, where the first capacitor is coupled to a terminal of a qubit device of the quantum circuit assembly; and
a switch arrangement, to operate the signal path in one of a first phase, a second phase, or a third phase, wherein:
in the first phase, the first capacitor is to charge to a first voltage, and the second capacitor is decoupled from the first capacitor,
in the second phase, the second capacitor is to charge to a second voltage, and the second capacitor is decoupled from the first capacitor, and
in the third phase, the second capacitor is coupled to the first capacitor.