US 12,248,800 B2
Virtualization of interprocessor interrupts
Gilbert Neiger, Portland, OR (US); Rajesh Sankaran, Portland, OR (US); and Hisham Shafi, Akko (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2021, as Appl. No. 17/561,433.
Claims priority of provisional application 63/189,616, filed on May 17, 2021.
Prior Publication US 2022/0365802 A1, Nov. 17, 2022
Int. Cl. G06F 9/455 (2018.01); G06F 13/24 (2006.01)
CPC G06F 9/45558 (2013.01) [G06F 13/24 (2013.01); G06F 2213/24 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of processor cores;
a local interrupt controller comprising:
an interrupt controller register; and
logic to, in response to a write from a virtual machine to the interrupt controller register, record an interprocessor interrupt in a first data structure configured by a virtual machine monitor and send a notification of the interprocessor interrupt to at least one of the plurality of processor cores,
wherein the interrupt controller register is accessed by software according to a method that depends on a mode of the local interrupt controller, wherein the mode comprises a first mode in which the interrupt controller register is accessed by the software through memory accesses to a specified address, and a second mode in which the interrupt controller register is accessed by the software through a write instruction to a different register.