US 12,248,793 B2
Monitoring transitions of a circuit
Ronald Nerlich, Dresden (DE); Mark Jung, Marzling (DE); Johann Zipperer, Unterschleißheim (DE); and Dietmar Walther, Eching (DE)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Sep. 12, 2023, as Appl. No. 18/465,213.
Application 18/465,213 is a continuation of application No. 17/123,407, filed on Dec. 16, 2020, granted, now 11,755,342.
Prior Publication US 2023/0418627 A1, Dec. 28, 2023
Int. Cl. G05B 1/03 (2006.01); G05B 19/045 (2006.01); G06F 8/34 (2018.01); G06F 9/448 (2018.01)
CPC G06F 9/4498 (2018.02) [G05B 19/045 (2013.01); G06F 8/34 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A circuit comprising:
a guard trigger circuit comprising:
a first input configured to receive a first state signal;
a second input configured to receive a second state signal;
a first logic gate coupled to the first input and the second input;
a second logic gate coupled to an output of the first logic gate; and
an output;
a reset synchronizer circuit comprising:
an input coupled to the output of the guard trigger circuit;
a clock input configured to receive a clock signal;
a first flip-flop coupled to the input and to the clock input; and
an output coupled to an output of the first flip-flop;
a timeout circuit comprising:
an input coupled to the output of the reset synchronizer circuit;
a clock input configured to receive the clock signal;
a first flip-flop coupled to the input and to the clock input; and
an output coupled to an output of the first flip-flop; and
a reset requestor circuit comprising:
a first input coupled to the output of the guard trigger circuit;
a second input coupled to the output of the timeout circuit;
a first logic gate coupled to the first input and the second input; and
an output coupled to an output of the first logic gate.