US 12,248,788 B2
Distributed shared memory
Prakash Bangalore Prabhakar, San Jose, CA (US); Gentaro Hirota, San Jose, CA (US); Ronny Krashinsky, Portola Valley, CA (US); Ze Long, San Jose, CA (US); Brian Pharris, Cary, NC (US); Rajballav Dash, San Jose, CA (US); Jeff Tuckey, Saratoga, CA (US); Jerome F. Duluk, Jr., Palo Alto, CA (US); Lacky Shah, Los Altos Hills, CA (US); Luke Durant, San Jose, CA (US); Jack Choquette, Palo Alto, CA (US); Eric Werness, San Jose, CA (US); Naman Govil, Sunnyvale, CA (US); Manan Patel, San Jose, CA (US); Shayani Deb, Seattle, WA (US); Sandeep Navada, San Jose, CA (US); John Edmondson, Arlington, MA (US); Greg Palmer, Cedar Park, TX (US); Wish Gandhi, Sunnyvale, CA (US); Ravi Manyam, San Ramon, CA (US); Apoorv Parle, San Jose, CA (US); Olivier Giroux, Santa Clara, CA (US); Shirish Gadre, Fremont, CA (US); and Steve Heinrich, Madison, AL (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Mar. 10, 2022, as Appl. No. 17/691,690.
Prior Publication US 2023/0289189 A1, Sep. 14, 2023
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/52 (2006.01); G06F 9/54 (2006.01); G06F 13/16 (2006.01); G06T 1/60 (2006.01)
CPC G06F 9/3851 (2013.01) [G06F 9/522 (2013.01); G06F 9/544 (2013.01); G06F 13/1663 (2013.01); G06T 1/60 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A processing system comprising:
a first semiconductor memory block co-located with at least one associated first processing core executing a first cooperative thread array (CTA) of a cooperative group array (CGA);
a second semiconductor memory block co-located with at least one associated second processing core executing a second CTA of the CGA; and
an interconnect operatively connecting the first processing core with the second processing core,
wherein the first CTA is enabled to access the second semiconductor memory block via the second processing core.