US 12,248,785 B2
Instruction length decoding
Polychronis Xekalakis, Barcelona (ES); and Sumit Ahuja, Mountain View, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 3, 2020, as Appl. No. 17/062,556.
Application 17/062,556 is a continuation of application No. 14/580,603, filed on Dec. 23, 2014, granted, now 10,795,681.
Prior Publication US 2021/0096866 A1, Apr. 1, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30149 (2013.01) [G06F 9/3808 (2013.01); G06F 9/382 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a data processor;
memory to store binary translator software code, wherein the binary translator software code is executable by the data processor to:
identify a stream of variable length instructions for execution by the data processor;
translate the stream of variable length instructions to identify words that include variable length instructions, wherein identifying the words comprises identifying a boundary separating a first word including a first number of instructions and a second word including a second number of instructions;
load the translated stream of variable length instructions into a set of instruction cache lines to be accessed by the data processor; and
a hardware decoder of the data processor is to access the translated stream of variable length instructions and decode the translated stream of variable length instructions for the data processor based on boundaries identified by the binary translator software code executed by the data processor, wherein decoding the translated stream comprises advancing the hardware decoder's read position from an instruction cache line within the set of instruction cache lines based on one mask to identify the boundary between the first word and the second word.