US 12,248,784 B2
Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture
Kenichi Tashiro, Tsukuba (JP); Hiroyuki Mizuno, Kashiwa (JP); and Yuji Umemoto, Tsuchiura (JP)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Feb. 18, 2020, as Appl. No. 16/793,422.
Application 16/793,422 is a division of application No. 16/194,668, filed on Nov. 19, 2018, granted, now 10,564,962.
Application 16/194,668 is a division of application No. 15/379,515, filed on Dec. 15, 2016, granted, now 10,133,569, issued on Nov. 20, 2018.
Application 15/379,515 is a division of application No. 14/215,412, filed on Mar. 17, 2014, granted, now 9,557,992, issued on Jan. 31, 2017.
Application 14/215,412 is a division of application No. 13/247,101, filed on Sep. 28, 2011, granted, now 8,713,293, issued on Apr. 29, 2014.
Application 13/247,101 is a division of application No. 12/125,431, filed on May 22, 2008, granted, now 8,055,886, issued on Nov. 8, 2011.
Claims priority of provisional application 60/949,426, filed on Jul. 12, 2007.
Prior Publication US 2020/0183685 A1, Jun. 11, 2020
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30065 (2013.01) [G06F 9/3004 (2013.01); G06F 9/3016 (2013.01); G06F 9/3001 (2013.01); G06F 9/30098 (2013.01)] 6 Claims
OG exemplary drawing
 
1. An electronic device comprising:
a bias value generator circuit having a counter register, the bias value generator circuit configured to supply a set of bias values in a range;
a pipeline register;
an instruction circuit coupled to the pipeline register and the bias value generator circuit and configured to:
receive a first instruction that specifies the range of the bias value generator circuit;
receive a second instruction having an operand; and
repeatedly issue the second instruction to the pipeline register by providing a set of instructions to the pipeline register that each include a micro-opcode based on the second instruction and a respective operand based on the operand of the second instruction and on a respective bias value of the set of bias values; and
a scan controller coupled to the counter register and the pipeline register.