US 12,248,783 B2
Frequency scaling for per-core accelerator assignments
Stephen T. Palermo, Chandler, AZ (US); Srihari Makineni, Portland, OR (US); Shubha Bommalingaiahnapallya, East Brunswick, NJ (US); Neelam Chandwani, Portland, OR (US); Rany T. Elsayed, Folsom, CA (US); Udayan Mukherjee, Portland, OR (US); Lokpraveen Mosur, Gilbert, AZ (US); and Adwait Purandare, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 15, 2023, as Appl. No. 18/369,082.
Application 18/369,082 is a continuation of application No. 16/933,369, filed on Jul. 20, 2020, granted, now 11,775,298.
Claims priority of provisional application 63/015,083, filed on Apr. 24, 2020.
Prior Publication US 2024/0111531 A1, Apr. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/3203 (2019.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30036 (2013.01) [G06F 9/3887 (2013.01); G06F 9/3888 (2023.08)] 24 Claims
OG exemplary drawing
 
1. A processor, comprising:
a plurality of cores to be selectively configured on a per-core basis to operate in a first mode associated with execution of a particular type of instructions of an instruction set and a second mode not associated with the particular type of instructions; and
power control circuitry to:
receive a request to pre-grant licenses to a number of cores of the plurality of cores to operate in the first mode,
determine a first plurality of frequency values at which the number of cores are to operate,
pre-grant the licenses to the number of cores, and
determine a second plurality of frequency values at which other cores of the plurality of cores are to operate,
wherein the first plurality of frequency values and the second plurality of frequency values are based, at least in part, on a maximum power budget supported by the processor.