US 12,248,782 B2
Accelerating processor based artificial neural network computation
Andrew Stevens, Neufinsing (DE); Wolfgang Ecker, Munich (DE); and Sebastian Prebeck, Munich (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Aug. 25, 2020, as Appl. No. 17/001,977.
Prior Publication US 2022/0066776 A1, Mar. 3, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 9/355 (2018.01); G06F 9/38 (2018.01); G06F 12/04 (2006.01); G06N 3/02 (2006.01)
CPC G06F 9/30036 (2013.01) [G06F 9/30038 (2023.08); G06F 9/3004 (2013.01); G06F 9/3552 (2013.01); G06F 9/3802 (2013.01); G06F 9/3891 (2013.01); G06F 12/04 (2013.01); G06F 2212/401 (2013.01); G06N 3/02 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for an artificial neural network (ANN), comprising:
determining, via a memory fetch device, a stream of addresses of packed data stored on a memory device and a suppression indicator, wherein the suppression indicator identifies a subset of addresses in the stream of addresses that are associated with generated packed data on the memory device;
fetching, via the memory fetch device, stored packed data from the memory device based on the stream of addresses and the suppression indicator, wherein the memory fetch device fetches the stored packed data from the memory device sequentially, wherein the memory fetch device processes the stored packed data sequentially;
generating, via the memory fetch device, generated data based on the suppression indicator; and
constructing, via the memory fetch device, formatted data from the stored packed data or the generated packed data based on a predefined data structure of a microcontroller.