US 12,248,762 B2
Processing-in-memory (PIM) devices
Choung Ki Song, Yongin-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jan. 11, 2021, as Appl. No. 17/145,761.
Application 17/145,761 is a continuation in part of application No. 17/090,462, filed on Nov. 5, 2020, granted, now 11,537,323.
Claims priority of provisional application 62/959,574, filed on Jan. 10, 2020.
Claims priority of provisional application 62/959,593, filed on Jan. 10, 2020.
Claims priority of provisional application 62/958,223, filed on Jan. 7, 2020.
Claims priority of application No. 10-2020-0006902 (KR), filed on Jan. 17, 2020.
Prior Publication US 2021/0223996 A1, Jul. 22, 2021
Int. Cl. G06F 7/544 (2006.01)
CPC G06F 7/5443 (2013.01) 21 Claims
OG exemplary drawing
 
1. A processing-in-memory (PIM) device comprising:
a data storage region including a first memory bank configured to store first data divided into a first portion and a second portion, and a second memory bank configured to store second data divided into a first portion and a second portion; and
an arithmetic circuit configured to perform multiplication and accumulation (multiplication/accumulation) (MAC) operations on the first data and the second data and output final MAC result data,
wherein the arithmetic circuit includes:
a first multiplication-addition circuit configured to perform a first multiplication-addition operation on the first portion of the first data and the first portion of the second data to output first multiplication addition data;
a second multiplication-addition circuit configured to perform a second multiplication-addition operation on the second portion of the first data and the second portion of the second data to output second multiplication addition data; and
an adder configured to add the first multiplication addition data from the first multiplication-addition circuit and the second multiplication addition data from the second multiplication-addition circuit to output third multiplication addition data,
wherein the first portion of first data and the second portion of first data correspond to elements of a row of a weight matrix, and the first portion of second data and the second portion of second data correspond to elements of a column of a vector matrix.